1. Field of the Invention
This invention relates to a synchronous semiconductor memory device and more particularly to a synchronous semiconductor memory device of fast random cycle system (FCRAM) having a function of performing reading/writing of random data with respect to a memory cell array at high speed and a test method thereof, and is used in a fast random cycle RAM (SDR-FCRAM) and a double data rate type fast random cycle RAM (DDR-FCRAM) having a data transfer rate which is twice that of the above RAM, for example.
2. Description of the Related Art
In order to enhance the data access speed of the DRAM and attain large data bandwidth, a synchronous DRAM (SDRAM) is proposed and put into practical use. Recently, in order to further increase the bandwidth, a double data rate SDRAM (DDR-SDRAM) operated at a data rate which is twice that of the SDRAM is proposed and commercialized. Thus, the bandwidth of the SDRAM is increased However, it is difficult to significantly reduce the random cycle time (tRC), that is, the cycle time of data access to a different row address since a certain time is required for the operation of data readout from the memory core, amplification operation and precharge operation.
In order to solve the above problem, a fast cycle RAM (FCRAM) in which access to the memory core and the precharge operation are pipelined to reduce the random cycle time tRC to half that of the conventional SDRAM or less is proposed and starts to be commercialized.
The fast cycle RAM is described in U.S. Pat. No. 6,426,915, for example.
First, the command system of the FCRAM is schematically explained. The command of the FCRAM includes a first command and a second command input in a cycle next to a cycle of the first command and various operations are determined based on the combination of the commands. The first command is a command used to start the operation of the row-system circuit and the second command is a command used to start the operation of the column-system circuit. Time tRCD from the time the first command is input to start the operation of the row-system circuit until the second command is input to start the operation of the column-system circuit is set as one clock cycle.
FIG. 1 is a diagram showing transition of operation states caused by the combination of the first and second commands of the FCRAM. FIGS. 2A and 2B are function tables showing pin inputs corresponding to command inputs of FIG. 1.
As shown in FIG. 1, in response to first command input next to the standby state (STANDBY), a row address is fetched and a read command (Read with Auto-close) RDA or write command (Write with Auto-close) WRA is directly given instead of the conventional row access command ACT which starts the operation of the peripheral row-system circuit. Then, as shown in the function tables of FIGS. 2A and 2B, a command input is received when a chip select signal /CS pin provided in the SDR/DDR-SDRAM is set to the “L” level. The read command and write command are distinguished according to the level of a signal supplied to an FN (function control) pin, which defines the type of a command. In this example, the FN pin is set to the “H” level at the read time and it is set to the “L” level at the write time.
Further, a division decoding row address of the sense amplifier can be given by use of the first command. However, since the number of pins of a standard package used in the SDR/DDR-SDRAM is limited, existing control pins are used as address pins to suppress an increase in the number of pins. In this example, a /WE (write enable) signal pin and /CAS (column address strobe) signal pin in the SDR/DDR-SDRAM are used as address pins A14, A13.
The command is determined based on the combination of the two pins of /CS (chip select signal) and FN (function control signal). The first command includes a write active (Write with Auto-Close: WRA) command in which /CS=“L” level and FN=“H” level and a read active (Read with Auto-Close: RDA) command in which /CS “L” level and FN=“L” level. The second command includes a lower address latch (LAL) command of /CS=“H” level and a mode register set (MRS) command and auto refresh (REF) command of /CS=“L” level. By the combination of the above commands, commands for a write operation, read operation, mode register set operation and auto refresh operation are input. Further, the row address and column address are fetched at the first command input time and second command input time, respectively.
In the FCRAM with the above configuration, since the write/read operation is determined by the first command, not only the operation of the peripheral circuit but also the operation of the memory core can be started at the same time as fetching of the row address. In this case, random access can be started earlier than in a case wherein the operation of the memory core is started based on the second command. Further, since it is sufficient only if the column address is fetched by use of the second command, the process of selecting a column selection line CSL and outputting data can be rapidly performed. Thus, data can be transferred to the peripheral portion early. Therefore, the precharge operation of a bit line can be performed earlier (the precharge timing can be advanced) after a word line is reset. That is, in the FCRAM, both of the random access time tRAC and random cycle time tRC can be reduced.
Next, the operation of the FCRAM is simply explained.
FIG. 3 is an operation waveform diagram for illustrating the operation of the FCRAM when the clock cycle time is short. In the FCRAM, the first and second commands are input in successive cycles. When a signal (command detection signal) bACTV used to start the operation of the row-system circuit is set to the “L” level in response to the first command, an activation signal BNK of a corresponding bank is set to the “H” level, a word line WL of a corresponding address is activated and cell data is read out to a bit line pair BL. As a result, a signal (column gating releasing signal) bCENB which permits the operation of the column-system circuit to be started is set to the “L” level.
On the other hand, the write/read operation and auto refresh/mode register set are detected in response to input of the second command. A second command detection signal bCOLACT is set at the “L” level to start the operation of the column-system circuit at the read/write time. In response to a signal CENBON which is generated by accepting the read/write operation when the second command is input, a column select signal is generated (the column selection line CSL is set to the “H” level). Further, in a corresponding column address, data on the bit line BL is read out at the read time and data is written onto the bit line BL at the write time.
The bank activation time is set by use of an internal timer and a signal FCTMR which terminates the bank activation operation is output in response to the “L” level of an output signal BNKTMR of the timer which is operated in response to an activation signal BNK of a corresponding bank. Then, when a preset period of time has elapsed after the activation operation was started, the activation signal BNK of the corresponding bank becomes deactivated and the row precharge operation is started.
When the clock cycle time is short, the column selection line CSL does not instantly accept switching of the second command detection signal bCOLACT to the “L” level and is switched to the “H” level after the “L” level of the column gating release signal bCENB of the row-system circuit is accepted. At this time, a series of operations of switching from the row system to the column system is performed and the severest condition is put on the time tRCD from the time the first command is input to start the operation of the row-system circuit until the second command is input to start the operation of the column-system circuit.
In the memory which performs the high-speed operation, the specification of the time tRCD is severe. In the upstream step, that is, in the die sort test in which the basic operation of the product is checked, it is important to screen and replace a bit having a small amount of readout signal from the memory cell by a redundancy bit and enhance the yield in the later step. In the die sort test, a clock of a cycle longer than the period of the normal operation is input, but in the synchronous DRAM, the screening operation is performed by inputting the second command in the time tRCD which is shorter than the time defined by the specification.
However, in the FCRAM, the time tRCD from the time the first command is input until the second command is accepted is defined by one clock cycle and, in the die sort test in which the clock cycle is longer, the test cannot be made by reducing the time tRCD and it is difficult to perform the screening operation.
FIG. 4 is an operation waveform diagram for illustrating the operation of the FCRAM when the condition of the clock cycle time in the die sort test or the like is alleviated. As is clearly understood from FIG. 4, since the condition of tRCD is alleviated, the column selection line CSL is instantly switched to the “H” level in response to the second command detection signal bCOLACT without waiting for the “L” level of the column gating release signal bCENB which makes a column control circuit operable after the operation of the row-system circuit is terminated.
That is, since the column selection line CSL is selected under a condition that the bit line BL/bBL is charged/discharged to a VBLH/VSS level to some extent, a test is made in a condition which is alleviated in comparison with the actual operation and there occurs a possibility that faulty products will be overlooked in the test.
As described above, in the conventional synchronous semiconductor memory device of fast random cycle system and the test method thereof, the clock signal having a long cycle which exceeds time specified by the normal specification is input when an entry is made into the test mode such as the die sort test in which the clock cycle time tCK is long. Therefore, it is difficult to make the screening test while the time tRCD from the time the first command is input to start the operation of the row-system circuit until the second command is input to start the operation of the column-system circuit is reduced.